Performance Impact of Memory Systems

Zoltan Somodi

Diploma Thesis Summer 2001
Supervisors: Irina Chihaia, Prof. Thomas Stricker
Institute for Computer Systems, ETH Zürich


Trace driven simulation is a common approach to studying virtual memory systems. Given a reference trace - a sequence of virtual memory addresses that are accessed by an executing program - a simulator can mimic the way the program uses the memory system. Unfortunately, address traces can be extremely large, easily exceeding the capacities of modern storage devices even for traced executions lasting only a few seconds.

The design goal of our tools is to produce compact traces which can be stored for later simulations. One method for trace reduction is to produce a trace of significant dynamic events. With this technique, not all addresses that are accessed by the program are recorded, but only those that cannot be statically reconstructed. The trace output by the instrumented program is a compact trace which needs expansion before it can be used by the trace consumer, the memory simulator in our case.


Some inherent architectural features posed difficulties or added complexity to the resulting code. An ISA that includes memory-to-memory operations such as Intel architecture has more instructions to instrument than does a load-store architecture such as SPARC which usually retrieves operands from the register file. The Intel ISA also includes string operations which can perform an indeterminate number of references per instruction.

As the new code is added to the instrumented code, the control instruction targets must be translated. Unfortunately, there are some control instructions for which the target cannot be calculated at instrumentation time.

The metrics used to evaluate the performance of our tools were the slowdown, the code expansion, the trace reduction factor, and the trace regeneration time. Our study shows that the performance of the abstract execution instrumentation depends strongly upon the regularity of the program's control flow and memory reference patterns. Numeric programs (OPAL in our study) with sequential access patterns and few conditional branches require less instrumentation than do non-numeric programs (such as SMV) with more irregular behavior.

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ETH Zürich: Department of Computer Science
Comments to Irina Chihaia <>
Date 25-10-2001