CLSimulator

Christoph Nadig

Semester Project Winter 1995/96
Supervisors: J. Supcik, Prof. N. Wirth
Institute for Computer Systems, ETH Zürich

Objectives

FPGAs have been used for a long time for research as well as for student exercices in digital electronics courses here at the ETH. There exists an add-on board for the Ceres workstation as well as for PC's carrying an Atmel AT6002 FPGA amongst other components. The FPGA is directly connected to the workstation system bus and can thus be programmed by special routines. There also exists a comfortable graphical editor that allows editing the internal FPGA design interactively. Unluckily only few of the Ceres workstations are equipped with this add-on board. Even worse, students also would like to do their exercices at home since the editor is available for WinOberon. This FPGA emulator now closes this gap.

Results

The simulation is performed using events which describe changes at outputs of logical elements like gates or latches. These events are always kept in a chronological order. The simulation loop takes the event that will take place soonest and delivers the new output signal to all affected (i.e. connected) inputs of other logical elements. Their outputs are then recalculated thus creating new events that will take place sometime later (depending of the propagation time of the appropriate logical element).

The simulation system has been written in Oberon-2 and uses its OOP elements like heritage and type-bound procedures. These features make the software very flexible and keeps it small. More logical functions or even more complex elements may be implemented very easy if needed in future. The resulting code is spread over six modules and has a total of aprox. 1400 lines of code. These modules replace one module of the editor which manages the interfacing and configuration of the add-on board on a Ceres workstation. This way, the user is not aware of whether he uses the real FPGA or the simulator. There is no fancy graphics at the moment, but this may easily be added to help in debugging designs.

The simulator has successfully tested with various example designs like multiplier with fast carry bit propagation, LIFOs/FIFOs, bit counters and simple memories.

Availability

The full report of the project is available as [ plain or gnu- compressed PostScript].
The Oberon sources are also available as [ plain or gnu- compressed TAR file].

[ CS-Department | Up ]
ETH Zürich: Department of Computer Science
Comments to Jacques Supcik <supcik@inf.ethz.ch>
9.2.1996