fct specifies the node's function, x and y are its operands, and val, u, v are used in various ways by different applications, such as PLD fuse map generators, FPGA tools, simulators, and HCL. Registers are represented by double nodes, where r.x is the register's clock, r.y.x its enable signal, and r.y.y its data input.
Named signals are represented by records of the derived data type
Variable = RECORD (Signal)
name: ARRAY 32 OF CHAR;
class: SHORTINT;
next, dsc: Variable
END ;
The field next establishes a linear list of named variables, i.e. the compiler's symbol table. dsc is used in the case of structured variables and points to its element variables. The field v.x of a variable v denotes the expression assigned to the variable.
The command HCL.Compile translates an Oberon-00 program into a Lola data structure. The command HCL.Show shows generated data structures in the form of linear lists.
The compiler HCL also generates auxiliary variables with internal names. They stand for elements in the sequencing state machine, and for subexpressions in arithmetic expressions. For example, the assignment z := (a + b) + c is decomposed into #1 := a + b, #2 := #1 + c, z := #2. Theses auxiliary variables do not enlarge the generated circuits, but merely introduce names for internal nodes of the data structure.
The software is available as a tar gzipped file or as an Oberon AsciiCoded file
ident = letter {letter | digit}.
integer = digit {digit}.
factor = ident | integer | "TRUE" | "FALSE" | "~" factor | "ODD" factor |
"(" expression ")" | "{" expression ":" expression "," expression "}".
term = factor {("*" | "/" | "&") factor}.
SimpleExpression = ["+"|"-"] term {("+"| "-" | "OR") term}.
expression = SimpleExpression [("=" | "#" | "<" | ">=" | "<=" | ">") SimpleExpression].
assignment = ident ":=" expression {"," ident ":=" expression}.
IfStatement = "IF" expression "THEN" StatementSequence ["ELSE" StatementSequence] "END".
WhileStatement = "WHILE" expression "DO" StatementSequence "END".
Statement = [assignment | IfStatement | WhileStatement].
StatementSequence = Statement {";" Statement}.
type = "BOOLEAN" | "INTEGER".
IdentList = ident {"," ident} ":" type.
declarations = ["CONST" {IdentList ";"}] "VAR" {IdentList ";"}.
module = "MODULE" ident ";" declarations
"BEGIN" StatementSequence "END" ident "." .