The Programmable Logic Device ispGAL22V10

N. Wirth

Circuits to be implemented by the popular GAL22V10 PLD can be described in Lola and mapped onto the device by the program GAL22V10. Configurations can be loaded and tested while the chip remains in place.

The PLD features an and/or matrix with 22 inputs and 10 outputs fed into its 10 macrocells. 12 of the 22 inputs come from input pins, and 10 are feedbacks from the macrocells. One of the inputs also serves as clock input. Signals (variables) are associated with signal numbers by position assignments in the Lola program. The numbers are 0 - 9 for macrocell outputs and 10 - 21 for inputs. (The number of the clock is 21).


Programs to be loaded into the PLD must comply with the following restrictions:

1. There can be at most 10 output variables.
2. Given n outputs, there can be at most 22-n input variables.
3. There are no local variables (exception: tri-state outputs, see below).
4. All assignments for the outputs must have one of the following forms, where F(x) stands for an expression of input and output variables. We recommend to use disjunctive normal form for F.
y := F(x)   y := ~F(x)   y := REG(F(x))   y := ~REG(F(x))
5. The number of terms in each expression is limited according to the resources of the device.

How to proceed

1. Specify the circuit as a Lola program.
2. Compile the module.    Lola.Compile *
3. Map the circuit onto the PLD. GAL22V10.Map
4. Load the mapped circuit (takes a few seconds). GAL22V10.Program
5. Test correct loading (optional). GAL22V10.Verify
6. Test the circuit using test programs.


MODULE Counter;
IN ci: BIT;
OUT q0, q1, q2, q3, q4, q5, q6, q7, co: BIT;
BEGIN q0 :: 0; q1 :: 1; q2 :: 2; q3 :: 3; q4 :: 4; q5 :: 5; q6 :: 6; q7 :: 7;
co :: 8; ci :: 10;
q0 := REG(q0 - ci);
q1 := REG(q1 - q0*ci);
q2 := REG(q2 - q1*q0*ci);
q3 := REG(q3 - q2*q1*q0*ci);
q4 := REG(q4 - q3*q2*q1*q0*ci);
q5 := REG(q5 - q4*q3*q2*q1*q0*ci);
q6 := REG(q6 - q5*q4*q3*q2*q1*q0*ci);
q7 := REG(q7 - q6*q5*q4*q3*q2*q1*q0*ci);
co := q7*q6*q5*q4*q3*q2*q1*q0*ci
END Counter.

Macrocells and Tri-state outputs

If a signal z is specified as INOUT, an auxiliary variable, say h, can be introduced to denote the signal at the register's output. No pin assignment is needed for h.

MODULE Toggle;
IN x, oe, ck: BIT;
BEGIN z :: 0; x :: 10; oe :: 11; ck :: 21;
h := REG(ck: x * ~h); z := oe | h
END Toggle.

Asynchronous Reset

All registers can be reset by specifying a reset signal in the Lola program as shown below. The text following the symbol RESET must be a term.

IN rst': BIT;
further declarations;
RESET ~rst';

Signal to Pin Number Assignments

sigpin sigpin sigpin sigpin
126 620 114 1711
225 719 125 1812
324 818 136 1913
423 917 147 2016
159 212 (ck)

The Interface for Programming the Chip

The interface for programming, i.e. for downloading the fuse map, uses a parallel port with address GAL. (The value of GAL is to be adjusted according to the computer being used). Bit 0 is SDI (serial data input), bit 1 is MODE, and bit 4 the SCLK (serial clock). For input, bit 2 represents SDO (serial data output). For further details, refer to the Programming Specifications of the GAL22V10 data book.


The software is available as a tar gzipped file or as an Oberon AsciiCoded file

[ CS-Department | Institut for Computer Systems | CAD Tools ]

ETH Zürich: Department of Computer Science
Comments to Jacques Supcik <>
May 26, 1998